MIPS R4000 Microprocessor User's Manual 33
Introduction
Primary Caches
The R4000 processor incorporates separate on-chip primary instruction
and data caches to fill the high-performance pipeline. Each cache has its
own 64-bit data path, and each can be accessed in parallel.
The R4000 processor primary caches hold from 8 Kbytes to 32 Kbytes; the
R4400 processor primary caches are fixed at 16 Kbytes.
Cache accesses can occur up to twice each cycle. This provides the integer
and floating-point units with an aggregate bandwidth of 1.6 Gbytes per
second at a MasterClock frequency of 50 MHz.
Secondary Cache Interface
The R4000SC (secondary cache) and R4000MC (multiprocessor) versions
of the processor allow connection to an optional secondary cache. These
processors provide all of the secondary cache control circuitry, including
error checking and correcting (ECC) protection, on chip.
The Secondary Cache interface includes:
• a 128-bit data bus
• a 25-bit tag bus
• an 18-bit address bus
• SRAM control signals
The 128-bit-wide data bus is designed to minimize cache miss penalties,
and allow the use of standard low-cost SRAM in secondary cache.
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