MIPS R4000 Microprocessor User's Manual 7
Introduction
1.4 R4000 Processor Configurations
The R4000 processor
†
is packaged in three different configurations. All
processors are implemented in sub-1-micron CMOS technology.
• R4000PC is designed for cost-sensitive systems such as
inexpensive desktop systems and high-end embedded
controllers. It is packaged in a 179-pin PGA, and does not
support a secondary cache.
• R4000SC is designed for high-performance uniprocessor
systems. It is packaged in a 447-pin LGA/PGA and includes
integrated control for large secondary caches built from
standard SRAMs.
• R4000MC is designed for large cache-coherent multiprocessor
systems. It is packaged in a 447-pin LGA/PGA and, in addition
to the features of R4000SC, includes support for a wide variety
of bus designs and cache-coherency mechanisms.
Table 1-1 lists the features in each of the three configurations (X indicates
the feature is present). R4400 processor enhancements are described in the
section following.
1.5 R4400 Processor Enhancements
In addition to the features contained in the R4000 processor, the R4400
processor has the following enhancements:
• fully functional Status pins (described in Chapter 10)
• Master/Checker mode (described in Chapter 16)
• larger primary caches (described in Processor General Features,
in this chapter)
• uncached store buffer (described in Chapter 3)
• divide-by-6 and divide-by-8 modes (described in Chapter 10)
• cache error bit, EW, added to the CacheErr register (described in
Chapter 5).
† Features of the R4400 processor that differ from the R4000 processor are noted throughout
this book; for instance, R4400 processor enhancements are listed in the next section.
Otherwise, references to the R4000 processor may be taken to include the R4400 processor.
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