Mips Technologies R4000 - Error Checking Operation; Secondary Cache Data Bus; System Interface; System Interface and Secondary Cache Data Bus

Chapter 16
412 MIPS R4000 Microprocessor User's Manual
Error Checking Operation
The processor verifies data correctness by using either the parity or the
SECDED code as it passes data from the System interface to the secondary
cache, or it moves data from the secondary cache to the primary caches or
to the System interface.
System Interface
The processor generates correct check bits for doubleword, word, or
partial-word data transmitted to the System interface. As it checks for
data correctness, the processor passes data check bits from the secondary
cache, directly without changing the bits, to the System interface if the
interface is set to ECC mode. If the System interface is set to parity mode,
the processor indicates a secondary cache ECC error by corrupting the
state of the SysCmdP signal.
The processor does not check data received from the System interface for
external updates and external writes. By setting the SysCmd(4) bit in the
data identifier, it is possible to prevent the processor from checking read
response data from the System interface.
The processor does not check addresses received from the System
interface, but does generate correct check bits for addresses transmitted to
the System interface.
The processor does not contain a data corrector; instead, the processor
takes a cache error exception when it detects an error based on data check
bits. Software, in conjunction with an off-processor data corrector, is
responsible for correcting the data when SECDED code is employed.
Secondary Cache Data Bus
The 16 check bits, SCDChk(15:0), for the 128-bit secondary cache data bus
are organized as 8 check bits for the upper 64 bits of data, and 8 check bits
for the lower 64 bits of data.
System Interface and Secondary Cache Data Bus
The 8 check bits, SysADC(7:0), for the System interface address and data
bus provide even-byte parity, or are generated in accordance with a
SECDED code that also detects any 3- or 4-bit error in a nibble. The 8 check
bits for each half of the secondary cache data bus are always generated in
accordance with the SECDED code.