Chapter 12
358 MIPS R4000 Microprocessor User's Manual
Secondary Cache Write Cycle Time
Behavior of the processor is undefined if, based on the secondary cache
write cycle time, data is delivered to the processor faster than the
processor can handle it. Secondary cache write cycle time is defined as the
sum of the parameters:
T
Wr1Dly
, T
WrSUp
, and T
WrRc
These parameters are defined in Chapter 9, Table 9-1.
The rate at which the processor transmits data to an external agent is
programmable at boot time through the boot-time mode control interface.
The transmit data rate can be programmed to any of the data rates and
data patterns listed in Table 12-6, as long as the programmed data rate
does not exceed the maximum rate the processor can handle, based on the
secondary cache write cycle time. The behavior of the processor is
undefined if a programmed transmit data rate exceeds the maximum the
processor can support.
Figure 12-41 shows a processor write request in which the processor
transmit data rate is programmed as one doubleword every two cycles,
using the data pattern DDxx.
Figure 12-41 Processor Write Request, Transmit Data Rate Reduced
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0 Data1 Data2 Data3
SysCmd Bus
Write CData CData CData CEOD
ValidOut*
ValidIn*
ExtRqst*
Release*
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