Chapter 4
64 MIPS R4000 Microprocessor User's Manual
As shown in Figures 4-2 and 4-3, the virtual address is extended with an
8-bit address space identifier (ASID), which reduces the frequency of TLB
flushing when switching contexts. This 8-bit ASID is in the CP0 EntryHi
register, described later in this chapter. The Global bit (G) is in the EntryLo0
and EntryLo1 registers, described later in this chapter.
Physical Address Space
Using a 36-bit address, the processor physical address space encompasses
64 gigabytes. The section following describes the translation of a virtual
address to a physical address.
Virtual-to-Physical Address Translation
Converting a virtual address to a physical address begins by comparing
the virtual address from the processor with the virtual addresses in the
TLB; there is a match when the virtual page number (VPN) of the address
is the same as the VPN field of the entry, and either:
• the Global (G) bit of the TLB entry is set, or
• the ASID field of the virtual address is the same as the ASID
field of the TLB entry.
This match is referred to as a TLB hit. If there is no match, a TLB Miss
exception is taken by the processor and software is allowed to refill the
TLB from a page table of virtual/physical addresses in memory.
If there is a virtual address match in the TLB, the physical address is
output from the TLB and concatenated with the Offset, which represents
an address within the page frame space. The Offset does not pass through
the TLB.
Virtual-to-physical translation is described in greater detail throughout
the remainder of this chapter; Figure 4-20 is a flow diagram of the process
shown at the end of this chapter.
The next two sections describe the 32-bit and 64-bit address translations.
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