Mips Technologies R4000 - CACHE Operations; Load Linked Store Conditional Operation

MIPS R4000 Microprocessor User's Manual 327
System Interface
Figure 12-14 R4400 Processor Cached and Uncached Store Sequence
Referring to Figure 12-14, suppose an external intervention or snoop is
issued to the R4400 processor while the uncached store is still in the store
buffer (the uncached store data has not yet been stored off-chip). The
cached store from Figure 12-14 has hit in the primary cache and is in the
tag check (TC) stage of the pipeline (see Chapter 3 for a description of the
pipeline stages). In this case, the external agent sees the state of the
internal caches after the cached store but before the result of the uncached
store is available off the chip. Figure 12-15 shows how a SYNC instruction
can force the uncached store to occur before the cached store.
Figure 12-15 R4400 Processor Cached and Uncached Stores, Using SYNC
CACHE Operations
The processor provides a variety of CACHE operations to maintain the
state and contents of the primary and secondary caches. During the
execution of the CACHE operation instructions, the processor can issue
either write requests or invalidate requests.
Load Linked Store Conditional Operation
Generally, the execution of a Load Linked Store Conditional instruction
sequence is not visible at the System interface; that is, no special requests
are generated due to the execution of this instruction sequence.
There is, however, one situation in which the execution of a Load Linked
Store Conditional instruction sequence is visible, as indicated by the link
address retained bit during a processor read request, as programmed by the
SysCmd(2) bit. This situation occurs when the data location targeted by a
Load Linked Store Conditional instruction sequence maps to the same
cache line to which the instruction area containing the Load Linked Store
Conditional code sequence is mapped. In this case, immediately after
executing the Load Linked instruction, the cache line that contains the link
SW r2, (r3) # uncached store
SW r4, (r5) # cached store
SW r2, (r3) # uncached store
SYNC
SW r4, (r5) # cached store