Mips Technologies R4000 - Config Register (16)

Chapter 4
90 MIPS R4000 Microprocessor User's Manual
The low-order byte (bits 7:0) of the PRId register is interpreted as a revision
number, and the high-order byte (bits 15:8) is interpreted as an
implementation number. The implementation number of the R4000
processor is 0x04. The content of the high-order halfword (bits 31:16) of
the register are reserved.
The revision number is stored as a value in the form y.x, where y is a major
revision number in bits 7:4 and x is a minor revision number in bits 3:0.
The revision number can distinguish some chip revisions, however there
is no guarantee that changes to the chip will necessarily be reflected in the
PRId register, or that changes to the revision number necessarily reflect
real chip changes. For this reason, these values are not listed and software
should not rely on the revision number in the PRId register to characterize
the chip.
Config Register (16)
The Config register specifies various configuration options selected on
R4000 processors; Table 4-12 lists these options.
Some configuration options, as defined by Config bits 31:6, are set by the
hardware during reset and are included in the Config register as read-only
status bits for the software to access. Other configuration options are
read/write (as indicated by Config register bits 5:0) and controlled by
software; on reset these fields are undefined.
Certain configurations have restrictions. The Config register should be
initialized by software before caches are used. Caches should be written
back to memory before line sizes are changed, and caches should be
reinitialized after any change is made.
Figure 4-16 shows the format of the Config register; Table 4-12 describes
the Config register fields.
Figure 4-16 Config Register Format
Config Register
2031
21
EW SC SMEP
1
19 18 1617 815
13
DBIB
1
42 0
CM EC
13
30 28 27
4
24
23 22
SB
21
SS
21
SW
1
BE
1
14
EM
1
13
EB
1
0
12
1
11
IC
3
96
DC
53
31
CU K0