Chapter 2
36 MIPS R4000 Microprocessor User's Manual
2.1 CPU Instruction Formats
Each CPU instruction consists of a single 32-bit word, aligned on a word
boundary. There are three instruction formats—immediate (I-type), jump
(J-type), and register (R-type)—as shown in Figure 2-1. The use of a small
number of instruction formats simplifies instruction decoding, allowing
the compiler to synthesize more complicated (and less frequently used)
operations and addressing modes from these three formats as needed.
Figure 2-1 CPU Instruction Formats
In the MIPS architecture, coprocessor instructions are implementation-
dependent; see Appendix A for details of individual Coprocessor 0
instructions.
op 6-bit operation code
rs 5-bit source register specifier
rt
5-bit target (source/destination) register or branch
condition
immediate 16-bit immediate value, branch displacement or
address displacement
target 26-bit jump target address
rd 5-bit destination register specifier
sa 5-bit shift amount
funct 6-bit function field
015162021252631
015162021252631
0252631
op
rs rt immediate
op target
functop rs rt
1110 6 5
rd sa
R-Type (Register)
J-Type (Jump)
I-Type (Immediate)
To Next Page
Loading...