Chapter 4
62 MIPS R4000 Microprocessor User's Manual
4.1 Translation Lookaside Buffer (TLB)
Mapped virtual addresses are translated into physical addresses using an
on-chip TLB.
†
The TLB is a fully associative memory that holds 48 entries,
which provide mapping to 48 odd/even page pairs (96 pages). When
address mapping is indicated, each TLB entry is checked simultaneously
for a match with the virtual address that is extended with an ASID stored
in the EntryHi register.
The address mapped to a page ranges in size from 4 Kbytes to 16 Mbytes,
in multiples of 4—that is, 4K, 16K, 64K, 256K, 1M, 4M, 16M.
Hits and Misses
If there is a virtual address match, or hit, in the TLB, the physical page
number is extracted from the TLB and concatenated with the offset to form
the physical address (see Figure 4-1).
If no match occurs (TLB miss), an exception is taken and software refills
the TLB from the page table resident in memory. Software can write over
a selected TLB entry or use a hardware mechanism to write into a random
entry.
Multiple Matches
If more than one entry in the TLB matches the virtual address being
translated, the operation is undefined. To prevent permanent damage to
the part, the TLB may be disabled if more than several entries match. The
TLB-Shutdown (TS) bit in the Status register is set to 1 if the TLB is
disabled.
† There are virtual-to-physical address translations that occur outside of the TLB. For
example, addresses in the kseg0 and kseg1 spaces are unmapped translations. In these
spaces the physical address is derived by subtracting the base address of the space from
the virtual address.
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