Mips Technologies R4000 - Secondary Cache Tag Bus; System Interface Command Bus

MIPS R4000 Microprocessor User's Manual 413
Error Checking and Correcting
Secondary Cache Tag Bus
The 7 check bits, SCTChk(6:0), for the secondary cache tag bus are
generated in accordance with the SECDED code, which also detects any 3-
or 4-bit error in a nibble.
The processor generates check bits for the tag when it is written into the
secondary cache and checks the tag whenever the secondary cache is
accessed.
The processor contains a corrector for the secondary cache tag; the tag
corrector is not in-line for processor accesses due to primary cache misses.
The processor traps when a tag error is detected on a processor access due
to a primary cache miss. Software, using the processor cache management
primitives, is responsible for correcting the tag. When executing the cache
management primitives, the processor uses the corrected tag to generate
write back addresses and cache state.
For external accesses, the tag corrector is in-line; that is, the response to
external accesses is based on the corrected tag. The processor still traps on
tag errors detected during external accesses to allow software to repair the
contents of the cache if possible.
System Interface Command Bus
In the R4000 processor, the System interface command bus has a single
parity bit, SysCmdP, that provides even parity over the 9 bits of this bus.
The SysCmdP parity bit is generated when the System interface is in
master state, but it is not checked when the System interface is in slave
state. In the R4400 processor, input parity is reported through the Fault*
pin.
When the System interface is set to parity mode, the processor indicates a
secondary cache ECC error by corrupting the state of the SysCmdP signal.