MIPS R4000 Microprocessor User's Manual 217
Initialization Interface
Cold Reset
A cold reset can begin anytime after the processor has read the
initialization data stream, causing the processor to start with the Reset
exception. For information about saving processor states, see the
description of the Reset exception in Chapter 5.
A cold reset requires the same sequence as a power-on reset except that the
power is presumed to be stable before the assertion of the reset inputs and
the deassertion of VCCOk.
To begin the reset sequence, VCCOk must be deasserted for a minimum
of at least 64 MasterClock cycles before reassertion.
Warm Reset
To execute a warm reset, the Reset* input is asserted synchronously with
MasterClock. It is then held asserted for at least 64 MasterClock cycles
before being deasserted synchronously with MasterClock. The processor
internal clocks, PClock and SClock, and the System interface clocks,
TClock and RClock, are not affected by a warm reset. The boot-time
mode control serial data stream is not read by the processor on a warm
reset. A warm reset forces the processor to start with a Soft Reset
exception. For information about saving processor states, see the
description of the Soft Reset exception in Chapter 5.
The master clock output, MasterOut, can be used to generate any reset-
related signals for the processor that must be synchronous with
MasterClock.
†
After a power-on reset, cold reset, or warm reset, all processor internal
state machines are reset, and the processor begins execution at the reset
vector. All processor internal states are preserved during a warm reset,
although the precise state of the caches depends on whether or not a cache
miss sequence has been interrupted by resetting the processor state
machines.
† Since MasterOut is undefined until after the serial PROM is read, reset logic must not
depend on MasterOut before the boot PROM is read.
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