MIPS R4000 Microprocessor User's Manual 349
System Interface
External Intervention Request Protocol
External intervention requests use a protocol similar to that of external
read requests, except that a cache line size block of data can be returned
along with an indication of the cache state for the cache line. The cache
state indication depends upon the state of the cache line and the value of
the data return bit in the intervention request command.
†
The data return bit indicates either return on dirty or return on exclusive:
• If the data return bit indicates return on dirty, and the cache line
that is target of the intervention request is in the dirty exclusive
or dirty shared state, the contents of the cache line are returned
in response to the intervention request.
• If the data return bit indicates return on exclusive, and the cache
line that is the target of the intervention request is in the clean
exclusive or dirty exclusive state, the contents of the cache line
are returned in response to the intervention request.
If neither of the two cases above are true, the response to the intervention
request does not include the contents of the cache line, but simply indicates
the state of the cache line that is the target of the intervention request.
The case in which the processor returns a cache line state, but not cache
line contents, is described in the following steps:
1. The external agent asserts ExtRqst* to arbitrate for the System
interface.
2. The processor releases the System interface to slave state by asserting
Release*.
3. The external intervention request is driven onto the SysCmd bus and
the address onto the SysAD bus. ValidIn* is asserted for one cycle.
4. The processor drives a coherent data identifier that indicates the state
of the cache line on the SysCmd bus and asserts ValidOut* for one
cycle.
5. The SysAD bus is not used during the data cycle.
6. The data identifier indicates a response data cycle that contains a last
data cycle indication.
† If the cache line that is the target of the intervention request is not present in the cache—
that is, the tag comparison for the cache line at the target cache address fails—the cache
line that is the target of the intervention request is considered to be in the invalid state.
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