Chapter 5
130 MIPS R4000 Microprocessor User's Manual
TLB Invalid Exception
Cause
The TLB invalid exception occurs when a virtual address reference
matches a TLB entry that is marked invalid (TLB valid bit cleared). This
exception is not maskable.
Processing
The common exception vector is used for this exception. The TLBL or
TLBS code in the ExcCode field of the Cause register is set. This indicates
whether the instruction, as shown by the EPC register and BD bit in the
Cause register, caused the miss by an instruction reference, load operation,
or store operation.
When this exception occurs, the BadVAddr, Context, XContext and EntryHi
registers contain the virtual address that failed address translation. The
EntryHi register also contains the ASID from which the translation fault
occurred. The Random register normally contains a valid location in which
to put the replacement TLB entry. The contents of the EntryLo register are
undefined.
The EPC register contains the address of the instruction that caused the
exception unless this instruction is in a branch delay slot, in which case the
EPC register contains the address of the preceding branch instruction and
the BD bit of the Cause register is set.
TLB Invalid exception processing is shown in Figure 5-17.
Servicing
A TLB entry is typically marked invalid when one of the following is true:
• a virtual address does not exist
• the virtual address exists, but is not in main memory (a page
fault)
• a trap is desired on any reference to the page (for example, to
maintain a reference bit)
After servicing the cause of a TLB Invalid exception, the TLB entry is
located with TLBP (TLB Probe), and replaced by an entry with that entry’s
Valid bit set.
To Next Page
Loading...