Chapter 7
196 MIPS R4000 Microprocessor User's Manual
Unimplemented Instruction Exception (E)
Any attempt to execute an instruction with an operation code or format
code that has been reserved for future definition sets the Unimplemented bit
in the Cause field in the FPU Control/Status register and traps. The operand
and destination registers remain undisturbed and the instruction is
emulated in software. Any of the IEEE Standard 754 exceptions can arise
from the emulated operation, and these exceptions in turn are simulated.
The Unimplemented Instruction exception can also be signaled when
unusual operands or result conditions are detected that the implemented
hardware cannot handle properly. These include:
• Denormalized operand, except for Compare instruction
• Quiet Not a Number operand, except for Compare instruction
• Denormalized result or Underflow, when either Underflow or
Inexact Enable bits are set or the FS bit is not set.
• Reserved opcodes
• Unimplemented formats
• Operations which are invalid for their format (for instance,
CVT.S.S)
NOTE: Denormalized and NaN operands are only trapped if the
instruction is a convert or computational operation. Moves do not trap
if their operands are either denormalized or NaNs.
The use of this exception for such conditions is optional; most of these
conditions are newly developed and are not expected to be widely used in
early implementations. Loopholes are provided in the architecture so that
these conditions can be implemented with assistance provided by
software, maintaining full compatibility with the IEEE Standard 754.
Trap Enabled Results: The original operand values are undisturbed.
Trap Disabled Results: This trap cannot be disabled.
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