MIPS R4000 Microprocessor User's Manual 69
Memory Management
32-bit User Mode (useg)
In User mode, when UX = 0 in the Status register, User mode addressing
is compatible with the 32-bit addressing model shown in Figure 4-4, and a
2-Gbyte user address space is available, labelled useg.
All valid User mode virtual addresses have their most-significant bit
cleared to 0; any attempt to reference an address with the most-significant
bit set while in User mode causes an Address Error exception.
The system maps all references to useg through the TLB, and bit settings
within the TLB entry for the page determine the cacheability of a reference.
64-bit User Mode (xuseg)
In User mode, when UX =1 in the Status register, User mode addressing is
extended to the 64-bit model shown in Figure 4-4. In 64-bit User mode, the
processor provides a single, uniform address space of 2
40
bytes, labelled
xuseg.
All valid User mode virtual addresses have bits 63:40 equal to 0; an
attempt to reference an address with bits 63:40 not equal to 0 causes an
Address Error exception.
Supervisor Mode Operations
Supervisor mode is designed for layered operating systems in which a
true kernel runs in R4000 Kernel mode, and the rest of the operating
system runs in Supervisor mode.
The processor operates in Supervisor mode when the Status register
contains the following bit-values:
• KSU = 01
2
• EXL =0
• ERL = 0
In conjunction with these bits, the SX bit in the Status register selects
between 32- or 64-bit Supervisor mode addressing:
• when SX = 0, 32-bit supervisor space is selected and TLB
misses are handled by the 32-bit TLB refill exception handler
• when SX = 1, 64-bit supervisor space is selected and TLB
misses are handled by the 64-bit XTLB refill exception handler
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