Mips Technologies R4000 - Trap Handlers for IEEE Standard 754 Exceptions

Chapter 7
198 MIPS R4000 Microprocessor User's Manual
7.6 Trap Handlers for IEEE Standard 754 Exceptions
The IEEE Standard 754 strongly recommends that users be allowed to
specify a trap handler for any of the five standard exceptions that can
compute; the trap handler can either compute or specify a substitute result
to be placed in the destination register of the operation.
By retrieving an instruction using the processor Exception Program Counter
(EPC) register, the trap handler determines:
• exceptions occurring during the operation
• the operation being performed
• the destination format
On Overflow or Underflow exceptions (except for conversions), and on
Inexact exceptions, the trap handler gains access to the correctly rounded
result by examining source registers and simulating the operation in
software.
On Overflow or Underflow exceptions encountered on floating-point
conversions, and on Invalid Operation and Divide-by-Zero exceptions, the
trap handler gains access to the operand values by examining the source
registers of the instruction.
The IEEE Standard 754 recommends that, if enabled, the overflow and
underflow traps take precedence over a separate inexact trap. This
prioritization is accomplished in software; hardware sets the bits for both
the Inexact exception and the Overflow or Underflow exception.