Mips Technologies R4000 - Flags

Chapter 7
190 MIPS R4000 Microprocessor User's Manual
7.3 Flags
A Flag bit is provided for each IEEE exception. This Flag bit is set to a 1 on
the assertion of its corresponding exception, with no corresponding
exception trap signaled.
The Flag bit is reset by writing a new value into the Status register; flags
can be saved and restored by software either individually or as a group.
When no exception trap is signaled, floating-point coprocessor takes a
default action, providing a substitute value for the exception-causing
result of the floating-point operation. The particular default action taken
depends upon the type of exception. Table 7-1 lists the default action taken
by the FPU for each of the IEEE exceptions.
Table 7-1 Default FPU Exception Actions
Field Description
Rounding
Mode
Default action
I
Inexact
exception
Any Supply a rounded result
U
Underflow
exception
RN
Modify underflow values to 0 with the sign of the
intermediate result
RZ
Modify underflow values to 0 with the sign of the
intermediate result
RP
Modify positive underflows to the format’s smallest positive
finite number; modify negative underflows to -0
RM
Modify negative underflows to the format’s smallest
negative finite number; modify positive underflows to 0
O
Overflow
exception
RN
Modify overflow values to
∞ with the sign of the
intermediate result
RZ
Modify overflow values to the format’s largest finite number
with the sign of the intermediate result
RP
Modify negative overflows to the format’s most negative
finite number; modify positive overflows to + ∞
RM
Modify positive overflows to the format’s largest finite
number; modify negative overflows to –
∞
Z
Division by
zero
Any Supply a properly signed ∞
V
Invalid
operation
Any Supply a quiet Not a Number (NaN)