Mips Technologies R4000 - Single Data Bit ECC Error

Chapter 16
420 MIPS R4000 Microprocessor User's Manual
Single Data Bit ECC Error
The following procedure detects and corrects a single data bit ECC error.
1. System A transmits:
Data(63:0) = 0x0000 0000 0000 0000
and
ECC(7:0) check code = 0000 0000
2
2. System B receives the following incorrect data:
Data(63:0) = 0x0000 0000 0000 0001
and
ECC(7:0) check code = 0000 0000
2
3. System B regenerates ECC for the received data. The correct ECC
check code for:
Data(63:0) = 0x0000 0000 0000 0001
is
ECC(7:0) = 0001 0011
2
4. A syndrome is generated by the XOR of the System A check bits,
0000 0000
2
, and the System B regenerated check bits, 0001 0011
2
.
The resulting syndrome is 0001 0011
2
. Since the syndrome has
three 1s, look for the column with three 1s in the parity check
matrix table.
5. Searching the matrix (Figure 16-1) shows that the syndrome, 0001
0011
2
, corresponds to data bit 0. This means the state of received
data bit 0 is incorrect.
6. To correct the error, the system inverts the state of the received
data bit 0 from a value of 1 to 0.