Mips Technologies R4000 - Organization of the Primary Instruction Cache (I-Cache)

MIPS R4000 Microprocessor User's Manual 249
Cache Organization, Operation, and Coherency
Organization of the Primary Instruction Cache (I-Cache)
Each line of primary I-cache data (although it is actually an instruction, it
is referred to as data to distinguish it from its tag) has an associated 26-bit
tag that contains a 24-bit physical address, a single valid bit, and a single
parity bit. Byte parity is used on I-cache data.
The R4000 processor primary I-cache has the following characteristics:
• direct-mapped
• indexed with a virtual address
• checked with a physical tag
• organized with either a 4-word (16-byte) or 8-word (32-byte)
cache line.
Figure 11-3 shows the format of an 8-word (32-byte) primary I-cache line.
Figure 11-3 R4000 8-Word Primary I-Cache Line Format
24
25 0
1
P
2324
V PTag
1
PTag Physical tag (bits 35:12 of the physical address)
V Valid bit
Data Cache data
P Even parity for the PTag and V fields
DataP Even parity; 1 parity bit per byte of data
8
71 06364
64
DataP Data
Data
DataP Data
DataP Data
DataP