Chapter 11
274 MIPS R4000 Microprocessor User's Manual
External Coherency Requests
If an external agent issues an external coherency request that conflicts with
an unacknowledged processor invalidate or update request, without
setting the cancellation bit, the system will operate in an undefined
manner. In this case, the processor has no indication of the conflict and
does not reevaluate the cache state to determine the correct action; it
simply waits for an acknowledge to its invalidate or update request as it
would for any invalidate or update request.
It is not possible for external coherency requests to conflict with processor
write requests, since the processor does not accept external requests while
a processor write request is in progress.
Tables 11-7 and 11-8 summarize the interactions between processor
coherency requests and conflicting external coherency requests, organized
by processor state. These two tables show the processor in one of the
following states:
Idle: no processor transactions are pending.
Read Pending: a processor coherent read request has been issued,
but the read response has not been received.
Potential Update Unacknowledged: a processor update request
has been issued while a processor coherent read request is pend-
ing but not yet acknowledged. By definition, therefore, the re-
sponse to the coherent read request has not been received.
Invalidate or Update Unacknowledged: a processor invalidate or
update request has been issued but has not yet been acknowl-
edged. By definition, no coherent read request is pending.
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