Chapter 3
44 MIPS R4000 Microprocessor User's Manual
3.1 CPU Pipeline Operation
The CPU has an eight-stage instruction pipeline; each stage takes one
PCycle (one cycle of PClock, which runs at twice the frequency of
MasterClock). Thus, the execution of each instruction takes at least eight
PCycles (four MasterClock cycles). An instruction can take longer—for
example, if the required data is not in the cache, the data must be retrieved
from main memory.
Once the pipeline has been filled, eight instructions are executed
simultaneously. Figure 3-1 shows the eight stages of the instruction
pipeline; the next section describes the pipeline stages.
Figure 3-1 Instruction Pipeline Stages
PCycle
(8-Deep)
Current
CPU
Cycle
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
MasterClock
Cycle
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