Chapter 12
342 MIPS R4000 Microprocessor User's Manual
External Arbitration Protocol
System interface arbitration uses the signals ExtRqst* and Release* as
described above. Figure 12-28 is a timing diagram of the arbitration
protocol, in which slave and master states are shown.
The arbitration cycle consists of the following steps:
1. The external agent asserts ExtRqst* when it wishes to submit an
external request.
2. The processor waits until it is ready to handle an external request,
whereupon it asserts Release* for one cycle.
3. The processor sets the SysAD and SysCmd buses to tri-state.
4. The external agent must wait at least two cycles after the assertion of
Release* before it drives the SysAD and SysCmd buses.
5. The external agent deasserts ExtRqst* two cycles after the assertion of
Release*, unless the external agent wishes to perform an additional
external request.
6. The external agent sets the SysAD and the SysCmd buses to tri-state
at the completion of an external request.
The processor can start issuing a processor request one cycle after the
external agent sets the bus to tri-state.
NOTE: Timings for the SysADC and SysCmdP buses are the same as
those of the SysAD and SysCmd buses, respectively.
Figure 12-28 Arbitration Protocol for External Requests
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr
Data0
SysCmd Bus
Cmd NEOD
ValidIn*
ExtRqst*
Release*
1
2
3
4
5
6
Master
Slave
Master
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