Chapter 5
114 MIPS R4000 Microprocessor User's Manual
XContext Register (20)
The read/write XContext register contains a pointer to an entry in the page
table entry (PTE) array, an operating system data structure that stores
virtual-to-physical address translations. When there is a TLB miss, the
operating system software loads the TLB with the missing translation
from the PTE array. The XContext register duplicates some of the
information provided in the BadVAddr register, and puts it in a form useful
for a software TLB exception handler. The XContext register is for use with
the XTLB refill handler, which loads TLB entries for references to a 64-bit
address space, and is included solely for operating system use. The
operating system sets the PTE base field in the register, as needed.
Normally, the operating system uses the Context register to address the
current page map, which resides in the kernel-mapped segment kseg3.
Figure 5-10 shows the format of the XContext register; Table 5-8 describes
the XContext register fields.
Figure 5-10 XContext Register Format
The 27-bit BadVPN2 field has bits 39:13 of the virtual address that caused
the TLB miss; bit 12 is excluded because a single TLB entry maps to an
even-odd page pair. For a 4-Kbyte page size, this format may be used
directly to address the pair-table of 8-byte PTEs. For other page and PTE
sizes, shifting and masking this value produces the appropriate address.
Table 5-8 XContext Register Fields
Field Description
BadVPN2
The Bad Virtual Page Number/2 field is written by hardware on a miss. It
contains the VPN of the most recent invalidly translated virtual address.
R
The Region field contains bits 63:62 of the virtual address.
00
2
= user
01
2
= supervisor
11
2
= kernel.
PTEBase
The Page Table Entry Base read/write field is normally written with a value
that allows the operating system to use the Context register as a pointer into
the current PTE array in memory.
XContext Register
31 30 4 363 0
31
PTEBase BadVPN2
27 4
0R
2
33 32
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