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General| Release Year | 1991 |
|---|---|
| Cores | 1 |
| Word Size | 64-bit |
| Data Bus Width | 64-bit |
| Address Bus Width | 32-bit |
| L1 Cache | 8 KB Instruction, 8 KB Data |
| FPU | Integrated |
| Process Technology | CMOS |
| Transistors | 1.2 million |
| Voltage | 5 V |
| Pipeline Stages | 8 |
| Architecture | MIPS |
| Clock Speed | 100 MHz |
| Performance | 1.0 DMIPS/MHz |
Discusses the structure of the manual, covering chapters on RISC development, CPU, pipeline, memory management, exceptions, FPU, signals, initialization, clock, cache, JTAG, and ECC.
Provides instructions on how to retrieve MIPS documents via FTP.
Discusses benefits derived from RISC design techniques, such as simpler design and chip-area resource allocation.
Outlines key R4000 features including 64-bit architecture, pipeline, MMU, caches, and FPU.
Describes the R4000's data formats and endianness configurations (big-endian, little-endian).
Details the three main instruction formats: I-Type, J-Type, and R-Type.
Lists the CPU registers: 32 general purpose registers, Program Counter (PC), and HI/LO registers.
Describes the eight-stage instruction pipeline and simultaneous execution of eight instructions.
Explains how pipeline flow is interrupted by cache misses, exceptions, or data dependencies, leading to stalls or slips.
Explains the TLB's role in caching virtual-to-physical address translations and its fully associative nature with 48 entries.
Details how the processor handles exceptions by suspending execution, entering Kernel mode, and using an exception handler.
Describes CP0 registers used in exception processing, including Context, BadVAddr, Status, and Cause registers.
Describes FPU features like 64-bit operation, load/store instructions, and its tightly-coupled coprocessor interface.
Lists IEEE 754 exceptions (Inexact, Underflow, Overflow, Invalid, Division by Zero) and the Unimplemented Operation exception.
Describes signals connecting the R4000 to system components, including SysAD, SysADC, SysCmd, and handshake signals.
Explains the three types of resets (Power-on, Cold, Warm) and the serial initialization interface.
Describes the core clock signals: MasterClock, MasterOut, SyncIn/SyncOut, PClock, SClock, TClock, and RClock.
Details the organization of primary caches and the optional secondary cache across R4000 models.
Describes the states of cache lines (Invalid, Shared, Dirty Shared, Clean Exclusive, Dirty Exclusive) and their availability across R4000 models.
Categorizes requests into processor requests and external requests, and describes their interaction with system events.
Lists external requests including read, write, invalidate, update, snoop, and intervention, and their protocols.
Details the maximum transmit data rates and patterns for secondary cache transfers, based on cycle times.
Describes the 4-word and 8-word read cycles, including timing diagrams and user-accessible parameters.
Explains boundary scan circuits as a series of shift register cells for testing ICs.
Lists the JTAG controller components: Instruction, Boundary-scan, Bypass registers, and TAP controller.
Describes how CPU hardware interrupts are caused by external write requests or dedicated pins.
Explains that NMI is caused by an external write request or a dedicated pin and is not level-sensitive.
Details the processor's use of parity (detection) and SECDED (single-bit correction/double-bit detection).
Explains parity as a simple error detection scheme using a parity bit to detect single-bit errors.
Describes SECDED ECC code for secondary cache data and tag, highlighting its single-bit correction and double-bit detection capabilities.
Divides CPU instructions into Load/Store, Computational, Jump/Branch, Coprocessor, and Special instruction classes.
Details the three main CPU instruction formats: I-Type, J-Type, and R-Type.
Describes the three basic FPU instruction format types: I-Type, M-Type, and R-Type.
Shows the physical pinout of the R4000PC and lists signal-to-pin correspondences.
Shows the physical pinout of the R4000MC/SC and lists signal-to-pin correspondences.
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