Mips Technologies R4000 - Mapping States between Caches

MIPS R4000 Microprocessor User's Manual 257
Cache Organization, Operation, and Coherency
Mapping States Between Caches
Secondary cache states correspond, or map, to primary cache states (this
mapping is listed in Table 11-6, later on in this chapter). For example, the
secondary cache shared and dirty shared states map to the primary cache
shared state.
Therefore, when the primary cache line is filled from the secondary cache,
the state of the secondary cache line is also mapped into the primary cache;
in the case described above, the shared or dirty shared secondary state is
mapped to the shared primary cache state.
As shown in Figure 11-8, a primary cache line in the R4000PC model can
be in either an invalid or dirty exclusive state. In the R4000SC model, a
primary cache line can be in the invalid, clean exclusive, or dirty exclusive
state. In the R4000MC model, the primary cache line can be invalid, clean
exclusive, dirty exclusive, or shared.
Figure 11-8 Primary Cache States Available to Each Type of Processor
R4000MC
Invalid State
R4000PC
Dirty Exclusive State
Invalid State
R4000SC
Clean Exclusive State
Dirty Exclusive State
Invalid State
Clean Exclusive State
Dirty Exclusive State
Shared State