Mips Technologies R4000 - Processor Null Write Request Protocol

Chapter 12
336 MIPS R4000 Microprocessor User's Manual
The processor pipeline stalls until one of the following occurs:
• IvdAck* or IvdErr* is asserted by the external agent. Assertion
of IvdAck* indicates a successful invalidation, and the
processor continues. IvdErr* causes a bus error exception.
• either an intervention, snoop, update, or invalidate request is
sent by the external agent, with the Invalidate or Update
Cancellation bit set, SysCmd(4) = 0, indicating the processor
invalidate or update request was cancelled.
If the processor update or invalidate request is cancelled, the instruction
that caused the processor request is re-executed. If the external request is
sent with SysCmd(4) = 1, indicating no cancellation, the processor, after
responding to the external request, stalls again until one of the two
conditions described above terminate the processor’s invalidate or update
request.
Processor Null Write Request Protocol
A processor null write request is issued with the System interface in
master state; the request consists of a single address cycle. The processor
drives a null command on the SysCmd bus and asserts ValidOut* for one
cycle. The SysAD bus is unused during the address cycle associated with
a null write request, and processor null write requests cannot be
controlled with either RdRdy* or WrRdy* signals. Figure 12-22 illustrates
a processor null write request.
Figure 12-22 Processor Null Write Request Protocol
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Unsd
SysCmd Bus
Null
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Master