Mips Technologies R4000 - Four Data Bit ECC Errors

Chapter 16
424 MIPS R4000 Microprocessor User's Manual
Four Data Bit ECC Errors
The following procedure detects four data bit errors that occur within a
nibble.
1. System A transmits:
Data(63:0) = 0x0000 0000 0000 0000
and
ECC(7:0) check code = 0000 0000
2
2. System B receives the following incorrect data:
Data(63:0) = 0x0000 0000 0000 1111
and
ECC(7:0) check code = 0000 0000
2
3. System B regenerates the ECC for the received data. The ECC
check code for:
Data(63:0) = 0x0000 0000 0000 1111
is
ECC(7:0) = 1111 0000
2
4. A syndrome is generated by the XOR of the System A check bits,
0000 0000
2
, and the System B regenerated check bits, 1111 0000
2
.
The resulting syndrome is 1111 0000
2
.
Since the resulting syndrome has four 1s (or an even number of
1s), this error is recognized as some variation of a double-bit error.
A 4-bit error within a nibble cannot be corrected.