MIPS R4000 Microprocessor User's Manual 303
System Interface
Rules for Processor Requests
The following rules apply to processor requests.
• After issuing a processor read request, either individually or as
part of a cluster, the processor cannot issue a subsequent read
request until it has received a read response.
• After issuing a processor update request, or after a potential
update request becomes compulsory, the processor cannot
issue a subsequent request until it has received an
acknowledge for the update request.
• After the processor has issued a write request, the processor
cannot issue a subsequent request until at least four cycles after
the issue cycle of the write request. This means back-to-back
write requests with a single data cycle are separated by two
unused system cycles, as shown in Figure 12-6.
Figure 12-6 Back-to-Back Write Cycle Timing
SCycle
1 2 3 4 5 6 7 8 9 10
SClock
SysAD Bus
Data Unused Unused Addr Data
WrRdy*
Addr
12
Write #1
Write #2
34
Cycles
To Next Page
Loading...