MIPS R4000 Microprocessor User's Manual 321
System Interface
Store Miss
When a processor store misses in both the primary and secondary caches,
the processor must obtain, from the external agent, the cache line that
contains the target location of the store. The processor examines the
coherency attribute in the TLB entry for the page (TLB page coherency
attributes are listed in Chapter 4) that contains the requested cache line to
see if the cache line is being maintained with either a write invalidate or a
write update cache coherency protocol.
The processor then executes one of the following requests:
• If the coherency attribute is either sharable or exclusive, a write
invalidate protocol is in effect, and a coherent block read that
requests exclusivity is issued.
• If the coherency attribute is update, a write update protocol is in
effect and a coherent block read request is issued.
• If the coherency attribute is noncoherent, a noncoherent block
read request is issued.
Table 12-4 shows the actions taken on a store miss to primary and
secondary caches.
To Next Page
Loading...