Chapter 12
360 MIPS R4000 Microprocessor User's Manual
An independent transmission on the SysAD bus follows this procedure:
1. The external agent requests mastership of the SysAD bus, to issue an
external request.
2. The processor releases the System interface to slave state.
3. If the processor is being used with a secondary cache, the external
agent issues a secondary cache release external null request to return
ownership of the secondary cache to the processor.
4. The external agent then allows the independent transmission to take
place on the SysAD bus, making sure that ValidIn* is not asserted
while the transmission is occurring.
5. When the transmission is complete, the external agent must issue a
System interface release external null request to return the System
interface to master state.
System Interface Endianness
The endianness of the System interface is programmed at boot time
through the boot-time mode control interface, and remains fixed until the
next time the processor mode bits are read. Software cannot change the
endianness of the System interface and the external system; software can
set the reverse endian bit to reverse the interpretation of endianness inside
the processor, but the endianness of the System interface remains
unchanged.
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