Mips Technologies R4000 - 32-Bit Mode Address Translation

MIPS R4000 Microprocessor User's Manual 65
Memory Management
32-bit Mode Address Translation
Figure 4-2 shows the virtual-to-physical-address translation of a 32-bit
mode address.
• The top portion of Figure 4-2 shows a virtual address with a
12-bit, or 4-Kbyte, page size, labelled Offset. The remaining 20
bits of the address represent the VPN, and index the 1M-entry
page table.
• The bottom portion of Figure 4-2 shows a virtual address with
a 24-bit, or 16-Mbyte, page size, labelled Offset. The remaining
8 bits of the address represent the VPN, and index the 256-
entry page table.
Figure 4-2 32-bit Mode Virtual Address Translation
28 11 0
20 12
2931
VPN
Offset
3239
ASID
8
Virtual Address with 1M (2
20
) 4-Kbyte pages
23
0
8 24
Offset
39
Virtual Address with 256 (2
8
)16-Mbyte pages
8 bits = 256 pages
20 bits = 1M pages
12
ASID
8
28 293132
VPN
24
Virtual-to-physical
translation in TLB
Bits 31, 30 and 29 of the virtual
address select user, supervisor,
or kernel address spaces.
Offset passed
unchanged to
physical
memory
Virtual-to-physical
translation in TLB
TLB
TLB
35 0
PFN
Offset
Offset passed
unchanged to
physical
memory
36-bit Physical Address