Mips Technologies R4000 - Backing up the Pipeline

Chapter 3
54 MIPS R4000 Microprocessor User's Manual
Backing Up the Pipeline
An example of pipeline back-up occurs in a data cache miss, in which the
late detection of the miss causes a subsequent instruction to compute an
incorrect result.
When this occurs, not only must the cache miss be serviced but the EX
stage of the dependent instruction must be re-executed before the pipeline
can be restarted. Figure 3-7 illustrates this procedure; a minus (–) after
the pipeline stage descriptor (for instance, EX–) indicates the operation
produced an incorrect result, while a plus (+) indicates the successful
re-execution of that operation.
Figure 3-7 Pipeline Overrun
Run Run Run Run Run Run Run Stl Stl Stl Stl Stl Run Run Run Run Run
Rst2 Rst1
IF IS RF EX DF DS TC DF DS TC WB
IF IS RF EX DF DS DF DS TC WB
IF IS RF EX DF DF DS TC WB
IF IS RF EX- RF EX+ DF DS TC WB
IF IS RF EX DF DS TC WB
Cycle
Restart
Load
ALU