Mips Technologies R4000 - Three Data Bit ECC Errors

MIPS R4000 Microprocessor User's Manual 423
Error Checking and Correcting
Three Data Bit ECC Errors
The following procedure detects three data bit errors that occur within a
nibble.
1. System A transmits:
Data(63:0) = 0x0000 0000 0000 0000
and
ECC(7:0) check code = 0000 0000
2
2. System B receives the following incorrect data:
Data(63:0) = 0x0000 0000 0000 0111
and
ECC(7:0) check code = 0000 0000
2
3. System B regenerates the ECC for the received data. The ECC
check code for:
Data(63:0) = 0x0000 0000 0000 0111
is
ECC(7:0) = 0111 0011
2
4. A syndrome is generated by the XOR of the System A check bits,
0000 0000
2
, and the System B regenerated check bits, 0111 0011
2
.
The resulting syndrome is 0111 0011
2
.
The resulting syndrome has five 1s. Since no four of the 1s are
contained in check bits (7:4) or check bits (3:0), three errors have
occurred within a nibble. Triple-bit errors within a nibble cannot
be corrected.