Chapter 11
258 MIPS R4000 Microprocessor User's Manual
11.5 Cache Line Ownership
A processor becomes the owner of a cache line after it writes to that cache
line (that is, by entering the dirty exclusive or dirty shared state), and is
responsible for providing the contents of that line on a read request.
There can only be one owner for each cache line.
The ownership of a cache line is set and maintained through the rules
described below.
• A processor assumes ownership of the cache line if the state of
the secondary cache line is dirty shared or dirty exclusive.
• A processor that owns a cache line is responsible for writing
the cache line back to memory if the line is replaced during the
execution of a Write-back or Write-back Invalidate cache
instruction. For read responses to a processor coherent read
request (both of these terms are defined in Chapter 12) in which
the data is returned in the dirty shared or dirty exclusive state,
the cache state is set when the last word of read response data
is returned. Therefore, the processor assumes ownership of the
cache line when the last word of response data is returned.
• For processor coherent write requests, the state of the cache
line changes to invalid if the cache line is replaced, or to either
clean exclusive or shared if the cache line is retained (provided
the cache line was written back to memory). In either case, the
cache state transition occurs when the last word of write data is
transmitted to the external agent. Therefore, the processor
gives up ownership of the cache line when the last word of
write data is transmitted to the external agent (Chapter 12
defines external agent).
• Memory always owns clean cache lines.
• The processor gives up ownership of a cache line when the
state of the cache line changes to invalid, shared, or clean
exclusive.
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