Mips Technologies R4000 - Floating-Point Load, Store, and Move Instructions; Load Delay and Hardware Interlocks; Transfers between FPU and CPU; Transfers between FPU and Memory

MIPS R4000 Microprocessor User's Manual 169
Floating-Point Unit
Floating-Point Load, Store, and Move Instructions
This section discusses the manner in which the FPU uses the load, store
and move instructions listed in Table 6-9; Appendix B provides a detailed
description of each instruction.
Transfers Between FPU and Memory
All data movement between the FPU and memory is accomplished by
using one of the following instructions:
• Load Word To Coprocessor 1 (LWC1) or Store Word From
Coprocessor 1 (SWC1) instructions, which reference a single
32-bit word of the FPU general registers
• Load Doubleword (LDC1) or Store Doubleword (SDC1)
instructions, which reference a 64-bit doubleword.
These load and store operations are unformatted; no format conversions
are performed and therefore no floating-point exceptions can occur due to
these operations.
Transfers Between FPU and CPU
Data can also be moved directly between the FPU and the CPU by using
one of the following instructions:
• Move To Coprocessor 1 (MTC1)
• Move From Coprocessor 1 (MFC1)
• Doubleword Move To Coprocessor 1 (DMTC1)
• Doubleword Move From Coprocessor 1 (DMFC1)
Like the floating-point load and store operations, these operations
perform no format conversions and never cause floating-point exceptions.
Load Delay and Hardware Interlocks
The instruction immediately following a load can use the contents of the
loaded register. In such cases the hardware interlocks, requiring
additional real cycles; for this reason, scheduling load delay slots is
desirable, although it is not required for functional code.