Chapter 11
266 MIPS R4000 Microprocessor User's Manual
Exclusive
Lines with an exclusive coherency attribute must be in a multiprocessor
environment. When the coherency attribute is exclusive, the processor
issues a coherent block read request that requests exclusivity for a load or
store miss to a location within the page.
Cache lines within the page are managed with a write invalidate protocol.
NOTE: Load Linked-Store Conditional instruction sequences must
ensure that the link location is not in a page managed with the
exclusive coherency attribute.
Cache Operation Modes
The R4000 processor supports the following two cache modes:
• secondary-cache mode (R4000MC and R4000SC models; for
R4000MC all five cache coherency attributes described above
are applicable, and for R4000SC only uncached and
noncoherent coherency attributes are applicable)
• no-secondary-cache mode (only uncached and noncoherent
coherency attributes are applicable).
Secondary-Cache Mode
In its secondary-cache mode, an R4000MC model provides a set of cache
states and mechanisms that implement a variety of cache coherency
protocols. In particular, the processor simultaneously supports both the
write-invalidate and write-update protocols.
No-Secondary-Cache Mode
A processor in no-secondary-cache mode supports the uncached and
noncoherent coherency attributes. These two attributes are described in
the section titled Cache Coherency Attributes in this chapter.
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