Mips Technologies R4000 - Pipelining the Exception Handling

Chapter 3
56 MIPS R4000 Microprocessor User's Manual
Pipelining the Exception Handling
Pipelining of interlock and exception handling is done by pipelining the
logical resolution of possible fault conditions with the buffering and
distributing of the pipeline control signals.
In particular, a half clock period is provided for buffering and distributing
the run control signal; during this time the logic evaluation to produce run
for the next cycle begins. Figure 3-9 shows this process for a sequence of
loads.
Figure 3-9 Pipelining of Interlock and Exception Handling
Clock
Phase
Load1:
12
DF DS TC WB
12 12121212
TagCk Resolve Buffer
DF DS TC WB
TagCk Resolve Buffer
DF DS TC WB
TagCk Resolve Buffer
Load2:
Load3: