MIPS R4000 Microprocessor User's Manual 335
System Interface
Figure 12-21 Processor Coherent Block Write Request Protocol (Delayed)
Processor Invalidate and Update Request Protocol
Processor invalidate request and update request protocols are the same as
a coherent word write request, except for the following:
• invalidate and update requests are controlled by RdRdy*,
while the write request is controlled by WrRdy*
• the single data cycle transfer is not used by an invalidate
request
Processor invalidate and update requests are acknowledged using the
signals IvdAck* and IvdErr*. The external agent drives either IvdAck* or
IvdErr* for one cycle to signal the completion of the current processor
update or invalidate request; IvdAck* occurs in parallel with requests on
the SysAD and SysCmd buses.
IvdAck* or IvdErr* can be driven at any time after a processor update or
invalidate request is issued, provided the update request is compulsory.
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0 Data1 Data2 Data3
SysCmd Bus
Write CData CData CData CEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
4
5
6
2
1
Master
3
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