Chapter 4
84 MIPS R4000 Microprocessor User's Manual
The TLB page coherency attribute (C) bits specify whether references to
the page should be cached; if cached, the algorithm selects between several
coherency attributes. Table 4-6 shows the coherency attributes selected by
the C bits.
Table 4-6 TLB Page Coherency (C) Bit Values
CP0 Registers
The following sections describe the CP0 registers, shown in Figure 4-7,
that are assigned specifically as a software interface with memory
management (each register is followed by its register number in
parentheses).
• Index register (CP0 register number 0)
• Random register (1)
• EntryLo0 (2) and EntryLo1 (3) registers
• PageMask register (5)
• Wired register (6)
• EntryHi register (10)
• PRId register (15)
• Config register (16)
• LLAddr register (17)
• TagLo (28) and TagHi (29) registers
C(5:3) Value Page Coherency Attribute
0 Reserved
1 Reserved
2 Uncached
3 Cacheable noncoherent (noncoherent)
4 Cacheable coherent exclusive (exclusive)
5 Cacheable coherent exclusive on write (sharable)
6 Cacheable coherent update on write (update)
7 Reserved
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