MIPS R4000 Microprocessor User's Manual 409
Error Checking and Correcting
The example above shows a single bit in Data(3:0) with a value of 1; this
bit is Data(1).
• In even parity, the parity bit is set to 1. This makes 2 (an even
number) the total number of bits with a value of 1.
• Odd parity makes the parity bit a 0 to keep the total number of
1-value bits an odd number—in the case shown above, the
single bit Data(1).
The example below shows odd and even parity bits for various data
values:
Data(3:0) Odd Parity Bit Even Parity Bit
0 1 1 0 1 0
0 0 0 0 1 0
1 1 1 1 1 0
1 1 0 1 0 1
Parity allows single-bit error detection, but it does not indicate which bit
is in error—for example, suppose an odd-parity value of 00011 arrives.
The last bit is the parity bit, and since odd parity demands an odd number
(1,3,5) of 1s, this data is in error: it has an even number of 1s. However it
is impossible to tell which bit is in error. To resolve this problem, SECDED
ECC was developed.
SECDED ECC Code
The ECC code chosen for processor secondary cache data and tag is single-
bit error correction and double-bit error detection (SECDED) code.
†
SECDED ECC code is an improvement upon the parity scheme; not only
does it detect single- and certain multi-bit errors, it corrects single-bit
errors.
† The 64-bit data code is a modification of one of the 64-bit codes proposed by M. Y. Hsiao,
to include the ability to detect 3- and 4-bit errors within a nibble. The 25-bit tag code was
created using the patterns observed in the 64-bit data code.
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