Mips Technologies R4000 - Initialization Interface Signals

Chapter 8
208 MIPS R4000 Microprocessor User's Manual
8.6 Initialization Interface Signals
The Initialization interface signals make up the interface by which an
external agent initializes the processor operating parameters. These
signals are available on each of the three processor configurations. Table
8-6 lists the Initialization interface signals.
Table 8-6 Initialization Interface Signals
†. A warm reset restarts processor, but does not affect clocks; it preserves the processor in-
ternal state. A description of warm reset is given in Chapter 9.
Name Definition Direction Description
ColdReset* Cold reset Input
This signal must be asserted for a
power on reset or a cold reset. The
clocks SClock, TClock, and RClock
begin to cycle and are synchronized
with the deasserted edge of
ColdReset*. ColdReset* must be
deasserted synchronously with
MasterOut.
ModeClock Boot mode clock Output
Serial boot-mode data clock output;
runs at the system clock frequency
divided by 256: (MasterClock/256).
ModeIn Boot mode data in Input Serial boot-mode data input.
Reset* Reset Input
This signal must be asserted for any
reset sequence. It can be asserted
synchronously or asynchronously for
a cold reset, or synchronously to
initiate a warm
†
reset. Reset* must be
deasserted synchronously with
MasterOut.
VCCOk Vcc is OK Input
When asserted, this signal indicates to
the processor that the +5 volt power
supply has been above 4.75 volts for
more than 100 milliseconds and will
remain stable. The assertion of
VCCOk initiates the initialization
sequence.