MIPS R4000 Microprocessor User's Manual 37
CPU Instruction Set Summary
Load and Store Instructions
Load and store are immediate (I-type) instructions that move data
between memory and the general registers. The only addressing mode
that load and store instructions directly support is base register plus 16-bit
signed immediate offset.
Scheduling a Load Delay Slot
A load instruction that does not allow its result to be used by the
instruction immediately following is called a delayed load instruction. The
instruction slot immediately following this delayed load instruction is
referred to as the load delay slot.
In the R4000 processor, the instruction immediately following a load
instruction can use the contents of the loaded register, however in such
cases hardware interlocks insert additional real cycles. Consequently,
scheduling load delay slots can be desirable, both for performance and
R-Series processor compatibility. However, the scheduling of load delay
slots is not absolutely required.
Defining Access Types
Access type indicates the size of an R4000 processor data item to be loaded
or stored, set by the load or store instruction opcode. Access types are
defined in Appendix A.
Regardless of access type or byte ordering (endianness), the address given
specifies the low-order byte in the addressed field. For a big-endian
configuration, the low-order byte is the most-significant byte; for a little-
endian configuration, the low-order byte is the least-significant byte.
†
The access type, together with the three low-order bits of the address,
define the bytes accessed within the addressed doubleword (shown in
Table 2-1). Only the combinations shown in Table 2-1 are permissible;
other combinations cause address error exceptions. See Appendix A for
individual descriptions of CPU load and store instructions.
† Data formats are described in Chapter 1.
To Next Page
Loading...