MIPS R4000 Microprocessor User's Manual 41
CPU Instruction Set Summary
Jump and Branch Instructions
Jump and branch instructions change the control flow of a program. All
jump and branch instructions occur with a delay of one instruction: that is,
the instruction immediately following the jump or branch (this is known
as the instruction in the delay slot) always executes while the target
instruction is being fetched from storage.
†
Overview of Jump Instructions
Subroutine calls in high-level languages are usually implemented with
Jump or Jump and Link instructions, both of which are J-type instructions.
In J-type format, the 26-bit target address shifts left 2 bits and combines
with the high-order 4 bits of the current program counter to form an
absolute address.
Returns, dispatches, and large cross-page jumps are usually implemented
with the Jump Register or Jump and Link Register instructions. Both are
R-type instructions that take the 32-bit or 64-bit byte address contained in
one of the general purpose registers.
For more information about jump instructions, refer to the individual
instruction as described in Appendix A.
Overview of Branch Instructions
All branch instruction target addresses are computed by adding the
address of the instruction in the delay slot to the 16-bit offset (shifted left
2 bits and sign-extended to 32 bits). All branches occur with a delay of one
instruction.
If a conditional branch likely is not taken, the instruction in the delay slot
is nullified.
For more information about branch instructions, refer to the individual
instruction as described in Appendix A.
† Taken branches have a 3 cycle penalty in this implementation. See Chapter 3 for more
information.
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