Chapter 16
414 MIPS R4000 Microprocessor User's Manual
SECDED ECC Matrices for Data and Tag Buses
The check matrices for data and tags, specifying the distribution of data
and check bits across nibbles, are shown in Figures 16-1 and 16-4.
The data bits in Figure 16-1 correspond to SysAD(63:0), SCData(127:64),
or SCData(63:0). The check bits in Figure 16-1 correspond to
SysADC(7:0), SCDChk(15:8), or SCDChk(7:0).
The check bits in Figure 16-4, shown later in this chapter, correspond to
SCTChk(6:0) and the data bits in Figure 16-4 correspond to SCTag(24:0).
The parity check matrices shown in these two figures generate the ECC
code for a fixed-width data word; they can also locate the data bit in error.
In Figure 16-1, the data word length is 64 bits; in Figure 16-4, the data word
length is 25 bits.
ECC Check Bits
The R4000 processor provides the following check bits: 16 check bits,
SCDChk(15:0), are used for the secondary cache data bus; 7 check bits,
SCTChk(6:0), are used for the secondary cache tag bus; 8 check bits,
SysADC(7:0), are used for the System interface address and data bus; a
single parity bit, SysCmdP, is used for the System interface command bus.
In the R4400 processor, the Fault* pin reports data parity or any ECC
errors received from the System interface during an external update or an
external write. The Fault* pin also reports errors among the address bits
received from the System interface. In each case, the full 64-bit data and 8-
bit ECC are significant. This checking is not affected by the state of the
disable bit [SysCmd(4)] in the data identifier. No exceptions are generated
for these checks.
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