MIPS R4000 Microprocessor User's Manual 49
The CPU Pipeline
3.5 Interlock and Exception Handling
Smooth pipeline flow is interrupted when cache misses or exceptions
occur, or when data dependencies are detected. Interruptions handled
using hardware, such as cache misses, are referred to as interlocks, while
those that are handled using software are called exceptions.
As shown in Figure 3-5, all interlock and exception conditions are
collectively referred to as faults.
Figure 3-5 Interlocks, Exceptions, and Faults
There are two types of interlocks:
• stalls, which are resolved by halting the pipeline
• slips, which require one part of the pipeline to advance while
another part of the pipeline is held static
At each cycle, exception and interlock conditions are checked for all active
instructions.
Because each exception or interlock condition corresponds to a particular
pipeline stage, a condition can be traced back to the particular instruction
in the exception/interlock stage, as shown in Figure 3-6. For instance, an
Illegal Instruction (II) exception is raised in the execution (EX) stage.
Tables 3-1 and 3-2 describe the pipeline interlocks and exceptions listed in
Figure 3-6.
Hardware
Exceptions
Software
Interlocks
Slips
Faults
Stalls
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