Mips Technologies R4000 - Page 80

Chapter 3
50 MIPS R4000 Microprocessor User's Manual
Figure 3-6 Correspondence of Pipeline Stage to Interlock Condition
State
Pipeline Stage
IF IS RF EX DF DS TC WB
Stall*
ITM ICM CPBE DCM
SXT WA
STI
*MP stalls can occur at any stage; they are not associated with any instruction or pipe stage
IF IS RF EX DF DS TC WB
Slip
LDI
MultB
DivB
MDOne
ShSlip
FCBsy
IF IS RF EX DF DS TC WB
Exceptions
ITLB Intr OVF DTLB DBE
IBE FPE TLBMod Watch
IVACoh ExTrap DVACoh
II DECCErr
BP NMI
SC Reset
CUn
IECCErr
Clock
PCycle
12121212121212 12