Mips Technologies R4000 - Summary of ECC Operations

Chapter 16
426 MIPS R4000 Microprocessor User's Manual
Summary of ECC Operations
ECC operations are summarized in Tables 16-1 through 16-4.
Table 16-1 Error Checking and Correcting Summary for Internal Transactions
† If error level (ERL bit of the Status register) is 1, the error is reported to the Fault* pin.
Bus
Secondary
Cache to
Primary
Cache
Primary
Cache to
Secondary
Cache
Uncached
Load
Uncached
Store
Processor or
Secondary Cache
Data
Checked;
Trap on Error
Primary
Cache parity
checked; Trap
on Error
From
System
Interface
Not
Checked
Secondary Cache
Data Check Bits
Checked;
Trap on Error
Generated NA NA
Secondary Cache Tag
and Check Bits
Checked; not
corrected in
Secondary
cache; Trap on
error
NA NA NA
System Interface
Address/Command
and Check Bits:
Transmit
NA NA Generated Generated
System Interface
Address/Command
and Check Bits:
Receive
NA NA Not
Checked;
reported to
the Fault*
pin
NA
System Interface Data NA NA Checked
Trap on
error
†
From
Processor
System Interface Data
Check Bits
NA NA Checked;
Trap on
Error
†
Generated