Chapter 11
268 MIPS R4000 Microprocessor User's Manual
Restarting the Processor
Strong ordering requires precise control of a processor restart.
Specifically, after completion of a processor coherency request, the system
must ensure the completion of any cache state changes before allowing a
processor restart.
The following sections describe processor restarts in a strong-ordered
system after a processor coherency request.
Restart after a Coherent Read Request
Unless a processor invalidate or update request is unacknowledged after
a coherent read request, the processor restarts (if sequential ordering is
enabled) after the last word in the block has been transmitted to the
processor.
Any external requests that must be completed before the read request is
finished must be issued to the processor before the read response is issued.
Restart after a Coherent Write Request
The processor restarts after the coherent write request is completed. That
is, the processor restarts after the last doubleword of data associated with
the write request has been transmitted to the external agent, unless a
processor read request is pending,
†
or a processor invalidate or update
request is unacknowledged.
Restart after an Invalidate or Update Request
Following an invalidate or update request, the processor restarts after the
external agent asserts IvdAck* or IvdErr*, unless a processor read request
is pending or the processor is processing an external request when either
IvdAck* or IvdErr* is asserted.
If either IvdAck* or IvdErr* is asserted during or after the first cycle that
the external agent asserts ExtRqst*, the processor accepts the external
request and completes any cache state changes associated with the
external request before restarting.
† That is, present but not yet executed.
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