Mips Technologies R4000 - External Requests

MIPS R4000 Microprocessor User's Manual 283
Cache Organization, Operation, and Coherency
Sample Cycle: Coherent Read Request
This section describes a multiprocessor system within which a coherent
read request cycle
†
services a secondary cache load miss. The system has
two processors, P
A
and P
B
, and two external agents linked to these
processors, external agent A (E
A
) and external agent B (E
B
). The external
agents connect the processors to a system bus. Each of the processors has
its own secondary cache.
The sample cycle follows the steps below (these steps are also numbered
in Figures 11-13, 11-14, and 11-15):
1. Processor B has a load miss within a sharable page.
2. Processor B issues a coherent read request (CRR) through E
B
.
3. The CRR is placed on the bus.
Figure 11-13 Cache Load Miss Cycle: Coherent Read Request
† Request Cycles are described in Chapter 12.
Coherent Read Request (CRR)
DE
Secondary
Cache A (S
A
)
System Bus
Secondary
Cache B (S
B
)
2
3
1
Processor
A (P
A
)
Processor
B (P
B
)
External
Agent B (E
B
)
Memory
External
Agent A (E
A
)
INV