Mips Technologies R4000 - Primary Cache States; Secondary Cache States

Chapter 11
256 MIPS R4000 Microprocessor User's Manual
Table 11-3 (cont.) Cache States
Primary Cache States
Each primary data cache line is in one of the following states:
• invalid
• shared
• clean exclusive
• dirty exclusive
Each primary instruction cache line is in one of the following states:
• invalid
• valid
Secondary Cache States
Each secondary cache line is in one of the following states:
• invalid
• shared
• dirty shared
• clean exclusive
• dirty exclusive
Cache
Line
State
Description
Where the
State is
Used
Available on
the Following
R4000 Models
Clean
Exclusive
A clean exclusive cache line contains valid
information and this cache line is not present in
any other cache. The cache line is consistent
with memory and is not owned by the
processor (see the section titled Cache Line
Ownership in this chapter).
Primary or
Secondary
Cache
R4000SC
R4000MC
Dirty
Exclusive
A dirty exclusive cache line contains valid
information and is not present in any other
cache. The cache line is inconsistent with
memory and is owned by the processor (see the
section titled Cache Line Ownership in this
chapter).
Primary or
Secondary
Cache
R4000PC
R4000SC
R4000MC